火狐体育官网入口(中国)有限公司致力于创造充满活力的工作环境并激发员工更好实现自我价值

职位名称 职位类型 工作地点 操作
Position Description: 
The position need to be developer for firmware, multimedia driver,  framework and optimization in Linux, Android, QNX or other RTOS . The candidate should be familiar with one of Graphic/Display, Video, Audio or Camera solution from user’s perspective. The position require the candidate working closely with SOC design/verification, Platform design and  Product team to work out the total solution from the bare-metal to driver and to application framework.
The engineer will be located in Beijing/Wuhan in SiEngine’s R&D SW team.

Required Skills: 
- 2+ years of software development in automotive, embedded system or mobile.
- Solid knowledge on mainstream DSP from Tensilica, Ceva, NXP and etc. 
- Solid knowledge on ARM architectures (v8- A, R or M) 
- Experience in driver and application development on RTOS such as FreeRTOS, ucOS, Nucleus and ThreadX. 
- Knowledge on audio/speech codecs such as: MP3, AAC, WMA, AC3, Dolby Digital, Auro 3D, DTS, FLAC, AMR(FR/HR).
- Experience in audio mixer for voice, media, BT, FMRadio and pre- and post-processing algorithms for quality enhancement - such as: EC/NS, EQ, ANC, ICC, AGC, SRC.
- Experience in compute engine accelerations, and experienced in voice trigger, speech recognition or AI/DL framework.
- Experience in interfaces and protocols as: S/PDIF, I2S/TDM, PCM, I2C and etc.
- Experience in Linux ALSA driver is a big plus.
- Good to follow software development flow, version control and bug trakcing with GIT, Jekins, Bugzilla or Jira. 

Position Description: 
The position need to be the lead or developer for embedded security software such as secure boot, TrustZone, Crypto Engine, FireWall . The candidate should be familiar with crypto algorithms, such as AES, SHA, RSA, ECDSA and so on; The candidate should understand common security mechanisms, such as encrypt, authentication. In particular, candidates should have a strong interest in security.  The candidate should have solid C/C++ development skills and debugging skills of GDB or Trace32 via JTAG. The position requires the candidate working closely with SOC design/verification, Platform design and Product team to work out the solution from the bare-metal to driver and to application framework.
The engineer will be located in WuHan/Beijing/Shanghai in SiEngine’s R&D SW team.

Required Skills: 
- 3~5 years of security development in embedded system or mobile system.
- Solid knowledge/skills of C/C++. 
- Solid knowledge on ARM architectures (v7/8- A, M) 
- Familiar with cryptographic algorithms: RSA, SHA, AES, ECDSA, SM2, SM3, SM4 and etc.
- Experiences in one of following areas: secure boot, TrustZone, crypto engine/HSM, Firewall. 
- Familiar with system, such as Linux/FreeRTOS/Android.
- Self-motived and ability to work independently in solving problem.

Education Requirement: 
- B.Sc and above degree from China top universities with major on Computer Science, Electronic Information Engineering, Telecommunication, EE or Automation etc
Position Description: 
The position need to be the lead or developer for embedded security software such as secure boot, TrustZone, Crypto Engine, FireWall . The candidate should be familiar with crypto algorithms, such as AES, SHA, RSA, ECDSA and so on; The candidate should understand common security mechanisms, such as encrypt, authentication. In particular, candidates should have a strong interest in security.  The candidate should have solid C/C++ development skills and debugging skills of GDB or Trace32 via JTAG. The position requires the candidate working closely with SOC design/verification, Platform design and Product team to work out the solution from the bare-metal to driver and to application framework.
The engineer will be located in WuHan/Beijing/Shanghai in SiEngine’s R&D SW team.

Required Skills: 
- 3~5 years of security development in embedded system or mobile system.
- Solid knowledge/skills of C/C++. 
- Solid knowledge on ARM architectures (v7/8- A, M) 
- Familiar with cryptographic algorithms: RSA, SHA, AES, ECDSA, SM2, SM3, SM4 and etc.
- Experiences in one of following areas: secure boot, TrustZone, crypto engine/HSM, Firewall. 
- Familiar with system, such as Linux/FreeRTOS/Android.
- Self-motived and ability to work independently in solving problem.

Education Requirement: 
- B.Sc and above degree from China top universities with major on Computer Science, Electronic Information Engineering, Telecommunication, EE or Automation etc
Position Description: 
The position need to be the lead or developer for embedded security software such as secure boot, TrustZone, Crypto Engine, FireWall . The candidate should be familiar with crypto algorithms, such as AES, SHA, RSA, ECDSA and so on; The candidate should understand common security mechanisms, such as encrypt, authentication. In particular, candidates should have a strong interest in security.  The candidate should have solid C/C++ development skills and debugging skills of GDB or Trace32 via JTAG. The position requires the candidate working closely with SOC design/verification, Platform design and Product team to work out the solution from the bare-metal to driver and to application framework.
The engineer will be located in WuHan/Beijing/Shanghai in SiEngine’s R&D SW team.

Required Skills: 
- 3~5 years of security development in embedded system or mobile system.
- Solid knowledge/skills of C/C++. 
- Solid knowledge on ARM architectures (v7/8- A, M) 
- Familiar with cryptographic algorithms: RSA, SHA, AES, ECDSA, SM2, SM3, SM4 and etc.
- Experiences in one of following areas: secure boot, TrustZone, crypto engine/HSM, Firewall. 
- Familiar with system, such as Linux/FreeRTOS/Android.
- Self-motived and ability to work independently in solving problem.

Education Requirement: 
- B.Sc and above degree from China top universities with major on Computer Science, Electronic Information Engineering, Telecommunication, EE or Automation etc

Position Description: 
The position will be a member of Android SW team for SOC SW release development. The position is expected to have experience with embedded software development, such as android HAL and Android framework development in automotive infotainment, home entertainment or mobile device domain.  
The candidate is also expected to be experienced with at least 2 out of the 3 following programming languages: C/C++/Java. 
The candidate is preferred to be familiar with popular android development & debug tools, including Git, Jenkins, Jira, ADB and so on. 
This position will be in SiEngine’s Shanghai/Wuhan office. 

Required Skills: 
- 2-10 years of software development with embedded system.
- Successful project experience with C, C++ or Java programming. 
- At least, Production proven skills in one of the following Android SW area: 
  Audio – audio flinger, audio policy, audio path, audio multiple devices support
  Automotive – Car service, Vehicle HAL, etc
  Camera – Multiple camera experience is plus
  Connectivity - especially WiFi module
  Interaction - key/Touching input, NN API,Peripherals, Sensors
  Media – OpenMAX, Android media player, etc
  Storage, Android OTA, Android boot optimization,
- Linux Kernel space and user space driver development skills is a plus.
- Android APP and APP framework development skills is a plus. Android CM experience is a plus.
- NN deep learning algorithm development or SW deployment experience is a plus.

Education Requirement: 
Bachelor’s degree and above from top universities, Major in EE, CS or related subjects.   Master’s degree and above, from 211, 985 universities, is a plus.
Job Description:
Develop system level safety architecture and concepts to make SiEgngine’s product to be used in safety critical system. Build development process and setup environment as per ISO26262 and quality management requirement in engineering team. Draft and refine safety documents to follow ISO26262 to achieve ASIL from A to D. Develop and maintain safety related SW such as test libs, drivers to help customer on quickly develop safety products based on SiEgine’s chip. Work closely with product team ,SoC design team on safety mechanism co-design, implementation and review. Do validation on safety related features to meet diagnostics coverage as required in respective ASIL level.  


Job Requirements:
- 2+ years of software development in automotive, embedded system or mobile.
- Have strong interests in function safety to design, analyse and solve critical safety related issue.
- Have validation and diagnostics design experience for at least one of following modules: power, clock, CPU core, Memory, Flash, BUS, Communication Channels etc.
- Familiarity with Failure Modes and Effect Analysis (FMEA) and Fault Tree Analysis (FTA) , Dependent Failure Analysis(DFA), experience on using tools to perform FMEA, FTA,DFA is preferred .
- Experiences on FSC and TSC, able to draft TSR, HSR and SSR and refine on TSR,HSR, SSR.
- Understanding software project management on reviewing, testing and quality management tasks, experiences on ASPICE and MISRA C is preferred. 
- Experiences on Safety Validation and FMEDA report is preferred.
- Experiences on  safety mechanisms such as STL, MemTest, PeriTest, ECC, CRC,  LBIST/MBIST and etc.
- Good to follow software development flow, version control and bug tracking with GIT, Jenkins, Bugzilla, or Jira
职位介绍
Develop system level safety architecture and concepts to make SiEgngine’s product to be used in safety critical system. Build development process and setup environment as per ISO26262 and quality management requirement in engineering team. Draft and refine safety documents to follow ISO26262 to achieve ASIL from A to D. Develop and maintain safety related SW such as test libs, drivers to help customer on quickly develop safety products based on SiEgine’s chip. Work closely with product team ,SoC design team on safety mechanism co-design, implementation and review. Do validation on safety related features to meet diagnostics coverage as required in respective ASIL level.  

任职要求:
- 2+ years of software development in automotive, embedded system or mobile.
- Have strong interests in function safety to design, analyse and solve critical safety related issue.
- Have validation and diagnostics design experience for at least one of following modules: power, clock, CPU core, Memory, Flash, BUS, Communication Channels etc.
- Familiarity with Failure Modes and Effect Analysis (FMEA) and Fault Tree Analysis (FTA) , Dependent Failure Analysis(DFA), experience on using tools to perform FMEA, FTA,DFA is preferred .
- Experiences on FSC and TSC, able to draft TSR, HSR and SSR and refine on TSR,HSR, SSR.
- Understanding software project management on reviewing, testing and quality management tasks, experiences on ASPICE and MISRA C is preferred. 
- Experiences on Safety Validation and FMEDA report is preferred.
- Experiences on  safety mechanisms such as STL, MemTest, PeriTest, ECC, CRC,  LBIST/MBIST and etc.
- Good to follow software development flow, version control and bug tracking with GIT, Jenkins, Bugzilla, or Jira
Job Description      
1. Responsible for Front-End chip implementation work from RTL2Netlist, including SOC/IP level Synthesis/STA/Formality check/Lint/CDC/Quality check.
2. Responsible for ASIC design methodology and flow development & optimization, interfacing with EDA vendors on technology.
3. Support Lint/CDC check, SDC/UPF writing.
4. Deliver constraints and closely co-work timing & power closure with P&R.

Job Requirement   
1. Hand on experience of Synthesis/Formality/STA/LEC/SDC/UPF/Netlist quality check.
2. Familiar with front-end EDA tools and flows (DCG, PT, Conformal, Formality, Spyglass, GCA)
3. Familiar with unix/linux and scripts (tcl, perl, makefile etc.)
4. Experience in highspeed interface IP, high performance Core is a plus.
5. Experience in dft or physical design is a plus.
6. A high-level of self-motivation and a proactive approach to solving problems.
Job Description      
1. Responsible for Front-End chip implementation work from RTL2Netlist, including SOC/IP level Synthesis/STA/Formality check/Lint/CDC/Quality check.
2. Responsible for ASIC design methodology and flow development & optimization, interfacing with EDA vendors on technology.
3. Support Lint/CDC check, SDC/UPF writing.
4. Deliver constraints and closely co-work timing & power closure with P&R.

Job Requirement   
1. Hand on experience of Synthesis/Formality/STA/LEC/SDC/UPF/Netlist quality check.
2. Familiar with front-end EDA tools and flows (DCG, PT, Conformal, Formality, Spyglass, GCA)
3. Familiar with unix/linux and scripts (tcl, perl, makefile etc.)
4. Experience in highspeed interface IP, high performance Core is a plus.
5. Experience in dft or physical design is a plus.
6. A high-level of self-motivation and a proactive approach to solving problems.
Job Description      
1. Responsible for Front-End chip implementation work from RTL2Netlist, including SOC/IP level Synthesis/STA/Formality check/Lint/CDC/Quality check.
2. Responsible for ASIC design methodology and flow development & optimization, interfacing with EDA vendors on technology.
3. Support Lint/CDC check, SDC/UPF writing.
4. Deliver constraints and closely co-work timing & power closure with P&R.

Job Requirement   
1. Hand on experience of Synthesis/Formality/STA/LEC/SDC/UPF/Netlist quality check.
2. Familiar with front-end EDA tools and flows (DCG, PT, Conformal, Formality, Spyglass, GCA)
3. Familiar with unix/linux and scripts (tcl, perl, makefile etc.)
4. Experience in highspeed interface IP, high performance Core is a plus.
5. Experience in dft or physical design is a plus.
6. A high-level of self-motivation and a proactive approach to solving problems.
Job Description    
1. Plan the EDA tool licensing, installation, manage disk/machines requirements, Library & IP release.
2. Build and enhance the design flow infrastructure of Soc design to improve design efficiency and quality.
3. Setup design environment related with Cadence, Synopsys, Mentor and other EDA tools.
4. Develop infrastructure for flow regression, automation flow and smart diagnosis solutions.
5. Work with design engineers to debug design/EDA environment issues.

Job Requirement 
1. 2+ years of hand-on experience in EDA/CAD related field.
2. Experienced with ASIC design flow.
3. Hand on experience on C++/Java, Perl, Python, TCL, shell, Makefile.
4. Experience with data collection, analysis and reporting techniques.
5. Strong analytical problem solving, team work and communication skills.
6. Proactive and self-motivated is must.

Job Description    
1. Plan the EDA tool licensing, installation, manage disk/machines requirements, Library & IP release.
2. Build and enhance the design flow infrastructure of Soc design to improve design efficiency and quality.
3. Setup design environment related with Cadence, Synopsys, Mentor and other EDA tools.
4. Develop infrastructure for flow regression, automation flow and smart diagnosis solutions.
5. Work with design engineers to debug design/EDA environment issues.

Job Requirement 
1. 2+ years of hand-on experience in EDA/CAD related field.
2. Experienced with ASIC design flow.
3. Hand on experience on C++/Java, Perl, Python, TCL, shell, Makefile.
4. Experience with data collection, analysis and reporting techniques.
5. Strong analytical problem solving, team work and communication skills.
6. Proactive and self-motivated is must.

Job Description    
1. Plan the EDA tool licensing, installation, manage disk/machines requirements, Library & IP release.
2. Build and enhance the design flow infrastructure of Soc design to improve design efficiency and quality.
3. Setup design environment related with Cadence, Synopsys, Mentor and other EDA tools.
4. Develop infrastructure for flow regression, automation flow and smart diagnosis solutions.
5. Work with design engineers to debug design/EDA environment issues.

Job Requirement 
1. 2+ years of hand-on experience in EDA/CAD related field.
2. Experienced with ASIC design flow.
3. Hand on experience on C++/Java, Perl, Python, TCL, shell, Makefile.
4. Experience with data collection, analysis and reporting techniques.
5. Strong analytical problem solving, team work and communication skills.
6. Proactive and self-motivated is must.

Job Description      
Work with Front-End design team and physical design team for super large-scale SoC chip physical implementation from RTL to GDS. Focus on physical design of deep sub-micron ultra large chip including block and chip level synthesis, floorplan, place and route, timing closure, physical verification, EM/IR signoff checks etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. 

Job Requirement   
1. Hands on experience in super large-scale SoC chip physical design, especially experience in 7nm FinFet technology and high-speed design implementation.
2. Solid knowledge and rich experience on synthesis, floorplan, place, CTS and routing, static timing analysis, EM/IR-drop and physical verification.
3. Project experience on hierarchical flow such as top-level partition, timing budgeting, pin assignment and Power Network Planning etc
4. Expertise with Synopsys/Cadence/Mentor EDA tools
5. Familiar with Unix/Linux environment and good at scripts
6. A high-level of self-motivation and a proactive approach to solving problems.
7. Good communication skills, strong interpersonal skills and the flexibility
8. Dedicated, hardworking, and good team player

Job Description
Work with Front-End design team and physical design team for super large-scale SoC chip physical implementation from RTL to GDS. Focus on physical design of deep sub-micron ultra large chip including block and chip level synthesis, floorplan, place and route, timing closure, physical verification, EM/IR signoff checks etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team.

Job Requirement
1. Hands on experience in super large-scale SoC chip physical design, especially experience in 7nm FinFet technology and high-speed design implementation.
2. Solid knowledge and rich experience on synthesis, floorplan, place, CTS and routing, static timing analysis, EM/IR-drop and physical verification.
3. Project experience on hierarchical flow such as top-level partition, timing budgeting, pin assignment and Power Network Planning etc
4. Expertise with Synopsys/Cadence/Mentor EDA tools
5. Familiar with Unix/Linux environment and good at scripts
6. A high-level of self-motivation and a proactive approach to solving problems.
7. Good communication skills, strong interpersonal skills and the flexibility
8. Dedicated, hardworking, and good team player

火狐体育官网入口(中国)有限公司