1. Work with SOC architecture team which has very large scale SOC experience from AMD/Intel/Marvell.
2. SOC micro architecture design according to MRD; SOC micro architecture analysis, optimization and simulation.
3. PCIE architecture design and system solution exploration.
4. PCIE3.0/4.0/5.0 controller and phy micro architecture design and optimization.
5. Chip interconnect design based on CXL or CCIX.
6. Read and understand the third-party IP datasheet, finish the IP integration design and RTL coding.
7. Perform RTL code quality check，CDC check，deliver the SDC & UPF file and support the IP/subsystem implementation.
8. Perform RTL-to-Netlist implementation using in-house implementation flow.
9. Function safety (Fusa) definition. Finish FSR, HSR, FMEA and FMEDA.
10. Co-work with DFT team to finish the test related logic implementation based on the IP requirement and support the test pattern development/verification.
11. Support the driver development of the software team, co-work with software team and system to finish the multimedia subsystem related system validation.
1. Hand on experience of logic design.
2. Be familiar with Frontend design & implementation flow，Such as：Lint，CDC check，logic synthesis，formal；Be familiar with related EDA tools.
3. Familiar with scripts (tcl, perl, makefile etc.).
4. Experience of PCIE3.0/4.0/5.0 protocal is a plus.
5. Experience of PCIE controller or phy design is a plus.
6. Experience of PCIE performance optimization is a plus.
7. Experience of CXL or CCIX is a plus.
8. Experience of clock/reset design is a plus.
9. Experience of low power design is a plus; be familiar with DVFS and power gating.
10. Experience of Fusa design is a plus.
11. Teamwork, A high-level of self-motivation and a proactive approach to solving problems.